1. Field of Invention
The present invention is related to memory testing and in particular test patterns to insure read signal integrity for a DDR DRAM.
2. Description of Related Art
A DDR DRAM is a memory chip that has been designed to provide high-speed reading and writing of data. In order to accomplish the high-speed, data is read or written using both edges of a clock. Thus for each clock cycle there is two bits of data being transferred to, or from, memory for each of two data words, where each data word comprises two four-bit segments. The signal lines for connecting the data from and to the sense amplifiers of the memory form a data bus and are routed on the memory chip in close proximity where wire elements of the data bus provide an opportunity for coupling between the high speed data signals. The ability of the bus circuitry to operate properly in a signal coupling environment is important for the memory chip to perform at high speed. Also, if a sequence of data bits of the same logical value is coupled onto a wire element of the data bus, an additional charge is built up on the wire and devices of the data path circuit that needs to be discharged when a data bit of opposite value is propagated on the wire element. A test to measure the ability of the driver of the wire element to overcome the additional charge is important to insure the operational integrity of the memory chip.
In U.S. Pat. No. 6,799,290 (Kirihata et al.) a method is directed to the testing of a data path of a memory device including a plurality of stages of the data path and the transfer of data along the data path. U.S. Pat. No. 6,813,696 (Kanada et al.) is directed to a method to read and write a memory array chip in synchronization with an externally supplied clock and to test the operation of the memory chip with conventional memory test equipment. U.S. Pat. No. 5,600,660 (Wolf) is directed to a method for determining the number of defective digital data bits transmitted over a data transmission path being tested.